The present invention relates to high speed telecommunication systems and more particularly to an improved dynamic time division multiplexing circuit wherein the shadow table which is memory space consuming is no longer required.
In telecommunication systems split in several subsystems where data are transmitted on a common media they share, the dynamic Time Division Multiplexing (TDM) access method is extensively used to exchange data between said subsystems. The TDM access method consists in splitting the time in time slots, each one corresponding to a logical channel, i.e., a connection between two subsystems. These logical channels, however, have different data throughputs and are only sporadically active, so that the time slot assignment must be dynamically performed via the use of programmable memories.
FIGS. 1a and 1b illustrate the fundamentals of the TDM access method. In FIG. 1a, there are shown six subsystems, labeled A to F, that exchange information via a bi-directional common media 10 (e.g., two transmission wires) at different times. For instance, the double arrow that links subsystems A and C illustrates a connection corresponding to a logical channel for full duplex data transmission there between at a given time and for a determined duration (to subsequently allow the other pairs of subsystems to communicate between themselves as suggested by the other double arrows). The maximum number of possible bi-directional logical connections is given by factorial 5 (5!), i.e., 120. In fact, the number of logical connections that is required in reality is much limited. Three double arrows are represented to illustrate full duplex connections only between subsystems A-C, B-E and D-F.
FIG. 1b shows an example of the assignment of the eight data bit positions labeled Bit1 to Bit8 (and more generally of n bit positions) of a TDM frame to three different logical channels X, Y and Z at a given time. These three logical channels (distinguished one from the another by their respective identifier: LC X, LC Y and LC Z) correspond to the full duplex connections between subsystems A-C, B-E and D-F in the example mentioned above. More generally, these identifiers can be understood as represented by a number coded on p bits, associated to any logical channel/connection between two subsystems. Two bit positions (Bit1-Bit2) are assigned to LC X, four bit positions (Bit3-Bit4-Bit5-Bit6) to LC Y and finally, two bit positions (Bit7-Bit8) to LC Z. This assignment thus defines the corresponding time allocation for each logical channel, three time slots in this example, labeled TimeslotX, TimeslotY and TimeslotZ respectively. A Time Slot Assignment (TSA) table 11 (describing the different time slots by specifying which logical channel each data bit position belongs to) can be then set up. Therefore, in the above described example wherein the 8-bit TDM frame is composed of three time slots of different sizes, the common media 10 that transports the serial data bits can be seen as composed of three logical channels of different throughputs (the throughput being proportional to the number of data bits). Because the content of the TSA table is time-dependent, the logical channel that is assigned to each of the TDM frame data bit position is variable. The data bits that fill the eight positions for each TDM frame are stored in dedicated First-In First-Out (FIFO) memories, each FIFO storing the data bits belonging to a determined logical channel. In other words, the content of each data bit position in the data stream transported on the common media 10 is determined by the logical channel assigned thereto, and this assignment dynamically changes.
A conventional technique of the prior art consists of providing a dynamic time slot assignment wherein two TSA tables are used at a given time, one being the active and the other the shadow table. While the active table is exploited by the time slot assignor, the shadow table may be updated by the application software to describe a new time slot assignment. Next, when appropriate, the tables are then swapped so that the shadow table is used as the active one and vice versa. FIG. 2 illustrates a standard dynamic time division multiplexing circuit 20 that implements such a conventional approach.
In FIG. 2, the active TSA table stored in memory block 21-1 contains a determined set of logical channel identifiers, e.g., LC X, LC Y and LC Z to remain consistent with the example described above by reference to FIG. 1b, while the shadow TSA table stored in memory block 21-2 contains another set thereof. The zero (“0”) value means that the corresponding data bit is not assigned to any logical channel. Each memory block has n fields. The two TSA tables stored in memory blocks 21-1 and 21-2 can be swapped, written, and read by a computer (or a microprocessor) under the control of an adequate application software as standard. These operations are performed through demultiplexer 22 which interfaces the computer and the memory blocks 21-1/21-2 via bi-directional buses 23 and 24a/24b respectively. Memory blocks 21-1 and 21-2 are connected to multiplexer 25 via buses 26a and 26b respectively, and in turn, multiplexer 25 is connected to the time slot assignor 27 via output bus 28. The time slot assignor 27 basically consists of a multiplexer driven by output bus 28, namely, the content of memory blocks 21-1 and 21-2 (only one can be accessed for a read operation at a given time) and a counter (not shown). The multiplexer is fed by a plurality of FIFOs and its output is the common media 10. The role of the time assignor 27 is to control the transmission of data bits on the common media 10 or the reception of data bits to load the FIFOs.
Assuming the TSA table stored in memory block 21-1 is made active and is exploited by the time slot assignor, the other one, stored in memory block 21-2, becomes the shadow TSA table and can be updated by the computer. While the time slot assignor reads the active TSA table to get the current time slot assignment (via the data path illustrated by gray arrow 29a), the computer edits the shadow TSA table for data updating (via the data path illustrated by double gray arrow 29b). The role of the computer is not to select which TSA table must be active, but rather to determine the time when a swapping operation is necessary. In case of full duplex serial transmission, two circuits 20 are necessary in reality; the first circuit controls the transmission of data bits from the FIFOs to the common media 10 for subsequent processing, and the second one controls the selective loading of data bits transported on the common media 10 in their respective FIFOs.
This approach is very flexible as it allows any kind of modification between the old and new time slot assignments, but it has the important drawback to require two memory blocks, typically SRAMs, to store the TSA tables which may be very large, consuming thereby a huge memory space therein. To date, it is classic to transmit data bits at 8.0192 Mbit/s, within a 125 μs time frame. In this case, a pattern is comprised of n=1024 bits (instead of 8 bits in the above example depicted in FIG. 1b), and thus two TSA tables, each one with 1024 entries, are required. On the other hand, in a typical application to telephony, it is also standard practice to have up to N=256 logical channels sharing the same common media 10, so that p=8 bits are required per logical channel to code its identifier. In such case, the memory space that is required to store either active or shadow TSA table would be n×p bits, i.e., 1024×8 bits.
The above described approach which basically requires two SRAM memory blocks, one demultiplexer circuit and one multiplexer circuit. Thus, there is a desire for a much more efficient approach which decreases the amount of memory space that is required, and/or obviates the use of said demultiplexer/multiplexer circuits.